GOA (Gate Driver on Array) skill is to integrate the TFT (Thin Film Transistor) of a gate driving circuit on the array substrate and to eliminate the integrated circuit part of the gate driving circuit located outside the array substrate. Accordingly, two aspects of material cost and process is considered to reduce the manufacture cost of the productions. GOA skill is a common gate driving circuit skill used in a present TFT-LCD (Thin Film Transistor-Liquid Crystal Display). The manufacture process is simple and provides great application possibilities. The functions of the GOA circuit mainly comprises: the present gate line outputs a high level signal with charging the capacitor of the shift register unit by using the high level signal outputted from the previous gate line, and then reset is achieved by using the high level signal outputted from the next gate line.
In 2D display mode, the GOA circuit transmission structure is that the present horizontal scanning line G(n) (n is a nature) directly transmits to the next horizontal scanning line G(n+1) thereafter. However, in 3D display mode, (which requires to respectively scanning displaying the images of the right eye and the left eye), the GOA circuit transmission structure is that the present horizontal scanning line G(n) transmits to the next second horizontal scanning line G(n+2) thereafter and the next horizontal scanning line G(n+1) keeps the same phase of the present horizontal scanning line G(n). Consequently, a floating period of one high frequency signal width redundantly appears between the next second horizontal scanning line G(n+2) and the present horizontal scanning line G(n) and leakage problem occurs.
For a large scale panel, once the GOA skill is utilized, as considering that the loadings of the wirings in the display area and GOA circuit area in the panel, the parasite capacitances and the resistances of element size are larger, multiple high frequency clock lines which at least six lines and even eight lines for some are generally utilized to reduce the RC loadings. For the GOA circuit having eight high frequency clock lines, the way of the utilized signal transmission is that N−4th level transmits the signal to the nth level in general.
Please refer to FIG. 1, which is a single level structural diagram of a GOA circuit commonly employed in panel display according to prior art. It comprises: a plurality of GOA units which are cascade connected, and a nth gate driver on array unit controls charge to a nth horizontal scanning line G(n) in a display area, and the nth gate driver on array unit comprises pull-up controlling part 100, a pull-up part 200, a transmission part 300, a first pull-down part 400 (Key pull-down part), a bootstrap capacitor part 500 and a pull-down holding part 600 (Pull-down holding part). The pull-up part 200, the first pull-down part 400, the pull-down holding part 600 and the bootstrap capacitor part 500 are respectively coupled to a Nth gate signal point Q(n) and the Nth horizontal scanning line G(n), and the pull-up controlling part 100 and the transmission part 300 are respectively coupled to the Nth gate signal point Q(n), and the pull-down holding part 600 is inputted with a DC low voltage VSS. The pull-up controlling part 100 comprises a first transistor T1, and the pull-up part 200 comprises a second transistor T2, the transmission part 300 comprises a third transistor T3, and the first pull-down part 400 comprises a fourth transistor T4 and a fifth transistor T5, and the bootstrap capacitor part 500 comprises a capacitor Cb; the first transistor T1 comprises a first gate g1, a first source s1 and a first drain d1, and the second transistor T2 comprises a second gate g2, a second source s2 and a second drain d2, and the third transistor T3 comprises a third gateg3, a third source s3 and a third drain d3, and the fourth transistor T4 comprises a fourth gate g4, a fourth source s4 and a fourth drain d4, and the fifth transistor T5 comprises a fifth gate g5, a fifth source s5 and a fifth drain d5; the first gate g1 is inputted with a N−4th transmission signal ST(N−4), and the first drain d1 is electrically coupled to a N−4th horizontal scanning line G(N−4), and the first source s1 is electrically coupled to gate signal point Q(N); the second gate g2 is electrically coupled to the gate signal point Q(N), and the second drain d2 is inputted with a mth high frequency clock CK(m), and the second source s2 is electrically coupled to the Nth horizontal scanning line G(N); the third gate g3 is electrically coupled to the gate signal point Q(N), and the third drain d3 is inputted with the mth high frequency clock CK(m), and the third source s3 outputs a Nth transmission signal ST(N); the fourth gate g4 is electrically coupled to the N+4th horizontal scanning line G(N+4), and the fourth drain d4 is electrically coupled to the Nth horizontal scanning line G(N), and the fourth source s4 is inputted with the DC low voltage VSS; the fifth gate g5 is electrically coupled to the N+4th horizontal scanning line G(N+4), and the fifth drain d5 is electrically coupled to the gate signal point Q(N), and the fifth source s5 is inputted with the DC low voltage VSS; an upper electrode plate of the capacitor Cb is electrically coupled to the gate signal point and a lower electrode plate of the capacitor Cb is electrically coupled to the Nth horizontal scanning line G(N). All of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are thin film transistors. The circuit structure as shown in FIG. 1 is a connection solution utilizing eight high frequency clock lines mainly for the large scale panel GOA skill. As shown in FIG. 1, the control signals of the pull-up controlling part 100 mainly come from the N−4th horizontal scanning line G(N−4). The control signals of the first pull-down part 400 come from the N+4th horizontal scanning line G(N+4).
For a large scale panel, the signal switching between 2D display and 3D display is also required for consideration. The clock signal settings in different modes must have certain differences. Please refer to FIG. 2a, which is a sequence diagram of the gate driving circuit shown in FIG. 1 as performing signal transmission in 2D mode. The gate driving circuit employs eight high frequency clocks CK1˜CK8, and two adjacent high frequency clocks are spaced a half pulse width apart. In FIG. 2a, the 1st high frequency clock CK1 corresponds to the first lifts of the N−4th horizontal scanning line G(N−4) and the gate signal point Q(N), and the 5th high frequency clock CK5 corresponds to the second lifts of the Nth horizontal scanning line G(N) and the gate signal point Q(N). In 2D mode, the signal transmission way of the eight high frequency clocks CK is that the N−4th horizontal scanning line G(N−4) transmits the signal to the Nth horizontal scanning line G(N). However, a larger time gap exist between the two signals without any signal functions, which leads to the certain leakage gap exists between the first lift and the second lift of the gate signal point Q(N). That is, the gate signal point Q(N) descends again after the gate signal point Q(N) is first lifted, which seriously influences the second bootstrap function of the gate signal point Q(N). Such leakage can be more serious if the operation is under high temperature condition and also influences the normal output of the Nth horizontal scanning line G(N). Please refer to FIG. 2b, which is a sequence diagram of the gate driving circuit shown in FIG. 1 as performing signal transmission in 3D mode. The gate driving circuit employs eight high frequency clocks CK1˜CK8, and the phases of the 1th high frequency clock CK1 and the 2nd high frequency clock CK2 are the same, and the phases of the 3rd high frequency clock CK3 and the 4th high frequency clock CK4 are the same, phases of the 5th high frequency clock CK5 and the 6th high frequency clock CK6 are the same, and the phases of the 7th high frequency clock CK7 and the 8th high frequency clock CK8 are the same, and two adjacent high frequency clocks with different phases are spaced a half pulse width apart. In FIG. 2b, the 1th high frequency clock CK1 and the 2nd high frequency clock CK2 with the same phase correspond to the first lifts of the N−4th horizontal scanning line G(N−4) and the gate signal point Q(N), and the 5th high frequency clock CK5 and the 6th high frequency clock CK6 with the same phase correspond to the second lifts of the Nth horizontal scanning line G(N) and the gate signal point Q(N). In 3D mode, with the 3D image display, two high frequency clocks CK will output simultaneously. There will be no leakage gap issue under circumstance that the signal transmission remains from the N−4th horizontal scanning line G(N−4) to the Nth horizontal scanning line G(N). The gate signal point Q(N) can be normally lifted without any obvious voltage level lost.
Therefore, once the GOA skill is utilized and the signal settings in 2D mode and 3D mode is required for consideration, a special gate driving circuit solution utilizing the GOA skill needs to be designed for solving the problems below: (1) in 2D mode, the larger leakage gap existing between the signal transmissions has to be compensated; (2) in 3D mode, the special gate driving circuit solution utilizing the GOA skill cannot influence such 3D signal transmission; (3) the gate driving circuit solution utilizing the GOA skill has to be guaranteed normal working in 2D display and 3D display.